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6-Bit Programmable 2-/3-Phase Synchronous Buck Controller ADP3197
FEATURES
Selectable 2-phase and 3-phase operation at up to 1 MHz per phase 10 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power good/crowbar blanking that supports on-the-fly VID code changes Digitally programmable 0.3750 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay
FUNCTIONAL BLOCK DIAGRAM
VCC 24 RT 9 RAMPADJ 10 SHUNT REGULATOR OSCILLATOR SET GND 15 EN 16 OD
UVLO SHUTDOWN
800mV EN 1
- + CURRENT BALANCING CIRCUIT
+ CMP - + CMP - + CMP -
RESET
23 PWM1
2.2V CSREF
- +
RESET 2-/3-PHASE DRIVER LOGIC RESET
22 PWM2
+ DAC - 250mV -
21 PWM3
CURRENT LIMIT PWRGD 2 DELAY CROWBAR 20 SW1 TTSENSE 31 19 SW2 THERMAL THROTTLING CONTROL 18 SW3
APPLICATIONS
Desktop PC power supplies for Next-generation AMD processors Voltage regulator modules (VRM)
VRHOT
32
14 CSCOMP ILIMIT DELAY 8 7 CURRENT MEASUREMENT AND LIMIT + - 13 CSSUM 12 CSREF
GENERAL DESCRIPTION
The ADP31971 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance, Advanced Micro Devices, AMD processors. It uses an internal 6-bit digital-to-analog converter (DAC) to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.3750 V and 1.55 V. It uses a multimode pulse-width modulation (PWM) architecture to drive the logic level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-phase or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. The ADP3197 supports a programmable slope function to adjust the output voltage as a function of the load current so it is always optimally positioned for a system transient. This can be disabled by connecting the LLSET pin to the CSREF pin. The ADP3197 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU.
1
IREF 17 COMP 5 PRECISION REFERENCE FBRTN 3 SOFT START CONTROL - + + -
4 FB
11 LLSET
6 SS
VID DAC
ADP3197
25 26 27 VID3 28 VID2 29 VID1 30 VID0 VID5 VID4
Figure 1.
The ADP3197 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3197 is specified over the extended commercial temperature range of 0C to 85C and is available in a 32-lead LFCSP.
Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06668-001
ADP3197 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Test Circuits....................................................................................... 9 Theory of Operation ...................................................................... 10 Start-Up Sequence...................................................................... 10 Phase Detection Sequence......................................................... 10 Master Clock Frequency............................................................ 11 Output Voltage Differential Sensing ........................................ 11 Output Current Sensing ............................................................ 11 Active Impedance Control Mode............................................. 11 Current Control Mode and Thermal Balance ........................ 11 Voltage Control Mode................................................................ 12 Current Reference ...................................................................... 12 Enhanced PWM Mode .............................................................. 12 Delay Timer................................................................................. 12 Soft Start ...................................................................................... 12 Current Limit, Short-Circuit, and Latch-Off Protection ...... 13 Dynamic VID.............................................................................. 13 Power-Good Monitoring........................................................... 13 Output Crowbar ......................................................................... 14 Output Enable and UVLO ........................................................ 14 Thermal Monitoring .................................................................. 14 Typical Application Circuit....................................................... 16 Applications Information .............................................................. 17 Setting the Clock Frequency..................................................... 17 Soft Start Delay Time................................................................. 17 Current-Limit Latch-Off Delay Times .................................... 17 Inductor Selection ...................................................................... 18 Current Sense Amplifier............................................................ 18 Inductor DCR Temperature Correction ................................. 19 Output Offset .............................................................................. 20 COUT Selection ............................................................................. 20 Power MOSFETs......................................................................... 21 Ramp Resistor Selection............................................................ 22 COMP Pin Ramp ....................................................................... 23 Current-Limit Setpoint.............................................................. 23 Feedback Loop Compensation Design.................................... 23 CIN Selection and Input Current di/dt Reduction.................. 25 Thermal Monitor Design .......................................................... 25 Shunt Resistor Design................................................................ 25 Tuning the ADP3197 ................................................................. 26 Layout and Component Placement ......................................... 27 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29
REVISION HISTORY
5/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADP3197 SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0C to 85C, unless otherwise noted 1 Table 1.
Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range 2 Accuracy Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Symbol VIREF IIREF VCOMP VFB Conditions Min Typ 1.5 15 Max Unit V A V mV mV LSB A A A MHz V/s mV nA V V A ns MHz kHz kHz kHz V mV A mV nA MHz V/s V V A ms mV k A % A V
RIREF = 100 k
14.25 0.05 -10 -78 -1 -9
15.75 4.4 10
Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 4) CSREF - LLSET = 80 mV IFB = 0.5 x IIREF FB forced to VOUT - 3% COMP = FB COMP = FB Relative to CSREF
-80 -7.5 65 500 20 25
IFB IFBRTN ICOMP GBW(ERR) VLLSET ILLSET VIL(VID) VIH(VID) IIN(VID)
-82 +1 -6 200
-250 -10
+250 +10 0.6
VIDx, VIDSEL VIDx, VIDSEL VID code change to FB change
1.4 -10 400 0.25 180 3 220
fOSC fPHASE
Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-off Delay Time CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR ILIMIT Bias Current ILIMIT Voltage
VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA)
TA = 25C, RT = 280 k, 3-phase TA = 25C, RT = 130 k, 3-phase TA = 25C, RT = 57.6 k, 3-phase RT = 280 k to GND RAMPADJ - FB, DAC=1.55 V
1.9 -50 1 -1.0 -10
200 400 800 2.0
2.1 +50 50 +1.0 +10
CSSUM - CSREF (see Figure 5) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF
10 10 0 0.05 500 8 -600 10 8 -4 9 1.09 +200 26 20 +4 11 1.33 3.5 3.5
ICSCOMP tOC(DELAY) VSWxCM RSWx ISWx ISWx IILIMIT VILIMIT
CDELAY = 10 nF
SWx = 0 V SWx = 0 V SWx = 0 V IILIMIT = 2/3 x IIREF RILIMIT = 121 k (VILIMIT = IILIMIT x RILIMIT)
17 12
10 1.21
Rev. 0 | Page 3 of 32
ADP3197
Parameter Maximum Output Voltage Current Limit Threshold Voltage Current Limit Setting Ratio DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current (Startup) Output Current (DAC Code Change) ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage OD Pulldown Resistor THERMAL THROTTLING CONTROL TTSENSE Voltage Range TTSENSE Bias Current TTSENSE VRHOT Threshold Voltage TTSENSE Hysteresis VRHOT Output Low Voltage POWER-GOOD COMPARATOR Overvoltage Threshold Undervoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY VCC DC Supply Current UVLO Turn On Current UVLO Threshold Voltage UVLO Threshold Voltage
1 2
Symbol VCL
Conditions VCSREF - VCSCOMP, RILIMIT = 121 k VCL/IILIMIT IDELAY = IIREF IDELAY(CL) = 0.25 x IIREF
Min 3 80
Typ 100 82.6 15 3.75 1.7 3.75 18.75 800 100 -1 2 160
Max 125
Unit V mV mV/V A A V A A mV mV A ms mV V k
IDELAY IDELAY(CL) VDELAY(TH) ISS(STARTUP) ISS(DAC) VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) VOL(OD) VOH(OD)
12 3.0 1.6 3 15 750 80
18 4.5 1.8 4.5 22.5 850 125
During startup, ISS(STARTUP) = 0.25 x IIREF DAC code change, ISS(DAC) = 1.25 x IIREF
EN > 950 mV, CDELAY = 10 nF
500
4
5 60
Internally limited
0 -135 665
-123 710 50 150
5 -111 755
V A mV mV mV mV mV mV mV mV ms s ns V mV mV V V mA mA V
VOL(VRHOT) VPWRGD(OV) VPWRGD(UV) VOL(PWRGD)
IVRHOT(SINK) = -4 mA Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V IPWRGD(SINK) = -4 mA CDELAY = 10 nF 100 200 190 -300 -310
300 300 310 -200 -190 300
250 250 -250 -250 150 2 250 200 1.8 300 160 5 5 6.5
VCROWBAR
Relative to FBRTN Relative to FBRTN IPWM(SINK) = -400 A IPWM(SOURCE) = +400 A VSYSTEM = 12 V, RSHUNT = 340 (see Figure 4)
1.75
1.85
VOL(PWM) VOH(PWM) VCC IVCC VUVLO VUVLO
500
4.0 4.65
5.55 25 11
VCC rising VCC falling
9 4.1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization; not tested in production.
Rev. 0 | Page 4 of 32
ADP3197 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC FBRTN PWM3, RAMPADJ SW1 to SW3 <200 ns All Other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 V to +6 V -0.3 V to +0.3 V -0.3 V to VCC + 0.3 V -5 V to +25 V -10 V to +25 V -0.3 V to VCC + 0.3 V -65C to +150C 0C to 85C 125C 100C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ESD CAUTION
Rev. 0 | Page 5 of 32
ADP3197 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VRHOT TTSENSE VID0 VID1 VID2 VID3 VID4 VID5
32 31 30 29 28 27 26 25
EN PWRGD FBRTN FB COMP SS DELAY ILIMIT
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADP3197
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
VCC PWM1 PWM2 PWM3 SW1 SW2 SW3 IREF
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 Mnemonic EN PWRGD FBRTN FB COMP SS DELAY ILIMIT RT RAMPADJ LLSET Description Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Power-Good Output. Open-drain output that signals when the output voltage is outside proper operating range. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. Error Amplifier Output and Compensation Point. Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time. Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off delay time, EN delay time, and PWRGD delay time. Current Limit Set Point. An external resistor from this pin to GND sets the current limit threshold of the converter. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables positioning. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the current sense amplifier and the positioning loop response time. Ground. All internal biasing and logic output signals of the device are referenced to this ground. Output Disable Logic Output. This pin is actively pulled low when EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, IILIMIT, and ITTSENSE. Current Balance Inputs. Inputs for measuring the current level in each phase. The SWx pins of unused phases should be left open.
12
CSREF
13 14 15 16 17 18 to 20
CSSUM CSCOMP GND OD IREF SW3 to SW1
Rev. 0 | Page 6 of 32
06668-005
NOTES 1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.
RT 9 RAMPADJ 10 LLSET 11 CSREF 12 CSSUM 13 CSCOMP 14 GND 15 OD 16
ADP3197
Pin No. 21 to 23 Mnemonic PWM3 to PMW1 VCC VID5 to VID0 TTSENSE VRHOT Description Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120. Connecting the PWM3 output to VCC causes that phase to turn off, allowing the ADP3197 to operate as a 2-phase or 3-phase controller. A 340 resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a Logic 0 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4). VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. Open-Drain Output. This output signals when the temperature at the monitoring point connected to TTSENSE exceeds the maximum operating temperature. This can be connected to the PROCHOT# (a PC system signal) output from the CPU.
24 25 to 30 31 32
Rev. 0 | Page 7 of 32
ADP3197 TYPICAL PERFORMANCE CHARACTERISTICS
7200 6400 5600
FREQUENCY (kHz)
4800 4000 3200 2400 1600 800 0 100 200 300 400 500 600 700 800 900
06668-015
0
RT (k)
Figure 3. Master Clock Frequency vs. RT
Rev. 0 | Page 8 of 32
ADP3197 TEST CIRCUITS
6-BIT CODE
12V
12V
ADP3197
680
24
32
VRHOT TTSENSE VID0 VID1 VID2 VID3 VID4 VID5
680
680 680
VCC FB
1.25V
1
1k 10nF 10nF
RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD
EN PWRGD FBRTN FB COMP SS DELAY ILIMIT
ADP3197
VCC PWM1 PWM2 PWM3 SW1 SW2 SW3 IREF
+
1F
100nF
4
10k
3
FBRTN LLSET
11
-
100k
V
12
121k
CSREF + GND
15
1V
20k
06668-002
VID DAC
100nF
VFB = FBV = 80mV - FBV = 0mV
Figure 4. Closed-Loop Output Voltage Accuracy
Figure 6. Positioning Voltage
12V
ADP3197
680 680
24
VCC CSCOMP
14
39k
100nF CSSUM
13
1k
12
CSREF CSCOMP - 1V 40
1V
15
Figure 5. Current Sense Amplifier VOS
06668-003
GND
VOS =
Rev. 0 | Page 9 of 32
06668-004
ADP3197 THEORY OF OPERATION
The ADP3197 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-phase and 3-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the AMD 6-bit CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3197 ensures a stable, high performance topology for * * * * * * * * * Balancing currents and thermals between phases High speed response at the lowest possible switching frequency and output decoupling Minimizing thermal switching losses by utilizing lower frequency operation Tight load line regulation and accuracy, if load line is selected High current output from having up to 3-phase operation Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component selection Flexibility in operation for tailoring design to low cost or high performance
0.8V ADP3197 EN VDELAY(TH) (1.7V)
DELAY
VVID SS
VVID VCC_CORE TD1
TD2 TD3
VID INVALID
VID VALID
Figure 7. System Start-Up Sequence
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their phase relationships are determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3197 operates as a 3-phase PWM controller. Connecting the PWM3 pin to the VCC pin programs 2-phase operation. While EN is low and prior to soft start, Pin PWM3 sinks approximately 100 A. An internal comparator checks each pin voltage vs. a threshold of 3 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 and PWM2 are low during the phase detection interval, which occurs during the first four clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 A current sink is removed and the outputs function as normal PWM outputs. If they are pulled to VCC, the 100 A current source is removed and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving external gate drivers, such as the ADP3120A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases.
START-UP SEQUENCE
The ADP3197 follows the start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first four clock cycles of TD2 are blanked from the PWM outputs and used for phase detection, as explained in the Phase Detection Sequence section. Then the soft start ramp is enabled (TD2) and the output comes up to the programmed DAC voltage. After TD2 has been completed and the PWRGD masking time (equal to VID on-the-fly masking) is finished, a second ramp on the DELAY pin sets the PWRGD blanking (TD3).
Rev. 0 | Page 10 of 32
06668-006
ADP3197
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3197 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 3. If the PWM3 pin is tied to VCC, then divide the master clock by 2 for the frequency of the remaining phases. The difference between CSREF and CSCOMP is then used as a differential input for the current limit comparator. This allows for the load line to be set independently of the current limit threshold. In the event that the current limit threshold and load line are not independent, the resistor divider between CSREF and CSCOMP can be removed and the CSCOMP pin can be directly connected to the LLSET pin. To disable voltage positioning entirely (that is, no load line), connect LLSET to CSREF. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is determined by external resistors so it can be made extremely accurate.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3197 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier. This maintains a worst-case specification of 10 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. The FB pin should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. The FBRTN pin should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the LLSET pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed-forward response.
OUTPUT CURRENT SENSING
The ADP3197 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element, such as the low-side MOSFET. This amplifier can be configured in the following ways, depending on the objectives of the system: * * * Output inductor DCR sensing without a thermistor for lowest cost Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements
CURRENT CONTROL MODE AND THERMAL BALANCE
The ADP3197 has individual inputs (SW1 to SW3) for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning, described in the Output Current Sensing section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an intentional current imbalance, if desired, such as when one phase may have better cooling and can support higher currents. Resistor RSW1 through Resistor RSW3 can be used for adjusting thermal balance (see the typical application circuit in Figure 10). It is best to add these resistors during the initial design, so be sure that placeholders are provided in the layout. To increase the current in any given phase, make RSWx for that phase larger (make RSWx = 0 for the hottest phase and do not change during balancing). Increasing RSWx to only 500 makes a substantial increase in phase current. Increase each RSWx value by small amounts to achieve balance, starting with the coolest phase first.
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. If required, an additional resistor divider connected between CSREF and CSCOMP, with the midpoint connected to LLSET, can be used to set the load line required by the microprocessor. The current information is then given as CSREF - LLSET. This difference signal is used internally to offset the VID DAC for voltage positioning.
Rev. 0 | Page 11 of 32
ADP3197
VOLTAGE CONTROL MODE
A high gain, high bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Figure 6 . If load line is selected, this voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FBRTN) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF/2) flows through RB into the FB pin and is used for setting the no load offset voltage from the VID voltage. The no load offset is positive with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP. The delay time is, therefore, set by the IREF current charging a capacitor from 0 V to 1.7 V. This DELAY pin is used for two delay timings (TD1 and TD3) during the start-up sequence. In addition, DELAY is used for timing the current limit latch-off, as explained in the Current Limit, Short-Circuit, and Latch-Off Protection section.
SOFT START
The soft start ramp rates for the output voltage are set up with a capacitor from the soft start (SS) pin to ground. During startup, the SS pin sources a current of 3.75 A. After startup, when a DAC code change takes place, the SS pin sinks or sources an 18.75 A current to control the rate at which the output voltage can transition up or down. During startup (after TD1 and the phase detection cycle have been completed), the SS time (TD2 in Figure 7) starts. The SS pin is disconnected from GND, and the capacitor is charged up to the programmed DAC voltage by the SS amplifier, which has an output current equal to 1/4 IREF (normally 3.75 A). The voltage at the FB pin follows the ramping voltage on the SS pin, limiting the inrush current during startup. The soft start time depends on the value of the initial DAC voltage and CSS. It is important to note that the DAC code needs to be set before the ADP3197 is enabled. Once the SS voltage is within 50 mV of the programmed DAC voltage, the power-good delay time (TD3) is started. Once TD2 has completed the SS current changes, it is changed to 18.75 A. If the programmed DAC code changes after startup, then the SS pin sources or sinks a current of 18.75 A to or from the SS cap until the SS voltage is within 50 mV of the newly programmed DAC voltage. If EN is taken low or VCC drops below UVLO, DELAY and SS are reset to ground in preparation for another soft start cycle. Figure 8 shows typical start-up waveforms for the ADP3197.
T
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor-toground programs the current, based on the 1.5 V output.
IREF = 1.5 V RIREF
Typically, RIREF is set to 100 k to program IREF = 15 A. The following currents are then equal to: IFB = 1/2 x (IREF) = 7.5 A IDELAY = IREF = 15 A ISS(STARTUP) =1/4 x (IREF) = 3.75 A ISS(DAC) = 5/4 x (IREF) = 18.75 A ILIMIT = 2/3 x (IREF) = 10 A ITTSENSE = 8 x (IREF) = 120 A
ENHANCED PWM MODE
Enhanced PWM mode is intended to improve the transient response of the ADP3197 to a load step-up. In previous generations of controllers, when a load step-up occurred, the controller had to wait until the next turn on of the PWM signal to respond to the load change. Enhanced PWM mode allows the controller to respond immediately when a load step-up occurs. This allows the phases to respond when the load increase transition takes place.
1
3
2
The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground. In UVLO or when EN is logic low, the DELAY pin is held at ground. After the UVLO and EN signals are asserted, the first delay time (TD1 in Figure 7) is initiated. A current flows out of the DELAY pin to charge CDLY. This current is equal to IREF, which is normally 15 A. A comparator monitors the DELAY voltage with a threshold of 1.7 V.
Rev. 0 | Page 12 of 32
4
CH1 1.00V CH3 1.00V
CH2 500mV CH4 10.0V
M2.00ms
A CH3
960mV
Figure 8. Typical Start-up Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: Power Good, Channel 4: Phase 1 Switch Node
06668-007
DELAY TIMER
ADP3197
CURRENT LIMIT, SHORT-CIRCUIT, AND LATCHOFF PROTECTION
The ADP3197 compares a programmable current limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During operation, the current from ILIMIT is equal to 2/3 IREF, giving 10 A normally. This current, through the external resistor, sets the ILIMIT voltage, which is internally scaled to give a current limit threshold of 82.6 mV/V. If the difference in voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. If the limit is reached and TD3 has completed, a latch-off delay time starts and the controller shuts down if the fault is not removed. The current limit delay time shares the DELAY pin timing capacitor with the start-up sequence timing. However, during current limit, the DELAY pin current is reduced to IREF/4. A comparator monitors the DELAY voltage and shuts off the controller when the voltage reaches 1.7 V. The current limit latchoff delay time is, therefore, set by the current of IREF/4, charging the delay capacitor from 0 V to 1.7 V. This delay is four times longer than the delay time during the start-up sequence. The current limit delay time starts only after TD3 has completed. If there is a current limit during startup, the ADP3197 goes through TD1 to TD3 and then starts the latch-off time. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.7 V threshold is reached, the controller returns to normal operation and the DELAY capacitor is reset to GND. The latch-off function can be reset either by removing and reapplying the supply voltage to the ADP3197 or by toggling the EN pin low for a short time. To disable the short-circuit latchoff function, an external resistor should be placed in parallel with CDLY. This prevents the DELAY capacitor from charging up to the 1.7 V threshold. The addition of this resistor causes a slight increase in the delay times. During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. An inherent per phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Typical overcurrent latch-off waveforms are shown in Figure 9.
1 T
2
3
4
CH1 1.00V CH3 5.00V
CH2 2.00V CH4 10.0V
M2.00ms
A CH1
660mV
Figure 9. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3197 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3197 detects the change and ignores the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the power-good and crowbar blanking functions for a minimum of 250 s to prevent a false power-good or crowbar event. Each VID change resets the internal timer.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits defined in the Power-Good Comparator section of the Specifications table, based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range. The PWRGD circuitry also incorporates an initial turn-on delay time (TD3) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS pin is within 50 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge up. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V. The PWRGD delay time is, therefore, set by a current of IREF charging a capacitor from 0 V to 1.7 V.
Rev. 0 | Page 13 of 32
06668-009
ADP3197
OUTPUT CROWBAR
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the lowside MOSFETs) when the output voltage exceeds the upper crowbar threshold. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
THERMAL MONITORING
The ADP3197 includes a thermal monitoring circuit to detect when a point on the VR has exceeded two different user-defined temperatures. The thermal monitoring circuit requires an NTC thermistor to be placed between TTSENSE and GND. A fixed current of eight times IREF (normally giving 123 A) is sourced out of the TTSENSE pin and into the thermistor. The current source is internally limited to 5 V. An internal circuit compares the TTSENSE voltage to a 0.81 V threshold and outputs an open-drain signal at the VRHOT outputs, respectively. The VRHOT open-drain output goes high once the voltage on the TTSENSE pin goes below the VRHOT thresholds and signals the system that an overtemperature event has occurred. Because the TTSENSE voltage changes slowly with respect to time, 50 mV of hysteresis is built into these comparators. The thermal monitoring circuitry does not depend on EN and is active when UVLO is above its threshold. When UVLO is below its threshold, VRHOT is forced low.
OUTPUT ENABLE AND UVLO
For the ADP3197 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, the EN pin must be higher than its 0.85 V threshold, and the DAC code must be valid. This initiates a system start-up sequence. If either UVLO or EN is less than its respective threshold, the ADP3197 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and forces the PWRGD and OD signals low. In the application circuit (see Figure 10), the OD pin should be connected to the OD inputs of the ADP3120A drivers. Grounding OD disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors.
Rev. 0 | Page 14 of 32
ADP3197
Table 4. VID Codes
OUTPUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 0.7625 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OUTPUT 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Rev. 0 | Page 15 of 32
ADP3197
L1 370nH 18A VIN 12V + U2 C11 ADP3120A 10nF C1 C2 D2 1N4148
1 2 3
2700F/16V/3.3A x 2 SANYO MV-WX SERIES + C12 4.7F
R4 2.2
C9 18nF
VIN RTN
BST
8 7 6
DRVH SW PGND 560F/4V x 6 L2 280nH/1.4m SANYO SEPC SERIES 5m EACH
Q1 IPD09N03L
IN OD
VCC(CORE) 0.375V TO 1.55V 100A TDC +
102
+
4
VCC
5
DRVL C25 Q3 IPD09N03L
C10 4.7F R5 2.2 Q2 IPD09N03L C13 18nF
C30
VCC(CORE) RTN 10F x 8 MLCC
TYPICAL APPLICATION CIRCUIT
VCC(SENSE) VSS(SENSE)
U3 C15 ADP3120A 10nF
C16 4.7F
1k
2 3
12V
IN
7 6 5
D3 1N4148
1
BST DRVH
8
Q4 IPD09N03L
SW PGND DRVL
L3 280nH/1.4m
OD
VCC
102
1F
4
RTH1 100k, 5% NTC C6 0.1F 680 + C4 1F R6 2.2 C17 18nF Q5 IPD09N03L C14 4.7F 680 C3 100F (C3 OPTIONAL)
VRMHOT
R2 169k 1%
Q6 IPD09N03L
FROM CPU
32 C19 U4 ADP3120A 10nF D4 1N4148
1 2 3
VTT I/O C20 4.7F
C5 1nF 1
BST IN U1
POWER GOOD
VRHOT TTSENSE VID0 VID1 VID2 VID3 VID4 VID5
DRVH SW PGND
8 7 6
Q7 IPD09N03L
ADP3197
OD
VCC
4
L4 280nH/1.4m 102
DRVL
5
RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND OD
06668-010
Figure 10. Typical Application of 3-Phase VR
EN PWRGD FBRTN FB COMP SS DELAY ILIMIT RSW11 RSW21 RIREF 100k RPH3 140k 1% RPH2 140k 1% RPH1 140k 1% RSW31 C18 4.7F
Rev. 0 | Page 16 of 32
VCC PWM1 PWM2 PWM3 SW1 SW2 SW3 IREF
RLIM 160k 1% RT 130k 1%
CB 630pF
CFB 16pF
RB 2k
RA CA CSS 630pF 18.7k 10nF
CDLY 18nF
Q8 IPD09N03L
Q9 IPD09N03L
RTH2 100k, 5% NTC
CCS1 1nF 5% NPO CCS2 RCS2 RCS1 1nF 35.7k 88.7k 5% NPO
C7 1nF
C8 1nF
R3 1
1
2
FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION. CONNECT NEAR EACH INDUCTOR.
ADP3197 APPLICATIONS INFORMATION
The design parameters for a typical AMD socket AM2 CPU application are as follows: * * * * * * * * * Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.300 V Duty cycle (D) = 0.108 Maximum static output voltage error (VSRER) = 50 mV Maximum dynamic output voltage error (VDRER) = 100 mV Error voltage allowed for controller and ripple (VRERR) = 20 mV Maximum output current (IO) = 110 A Maximum output current step (IO) = 70 A Static output droop resistance (RO) based on * No load output voltage set at upper output voltage limit VONL = VVID + VSERR - VRERR = 1.330 V * Full load output voltage set at lower output voltage limit VOFL = VVID - VSERR + VRERR = 1.270 V * RO = (VONL - VOFL)/IO = (1.33 V - 1.27 V)/110 A = 0.545 m Dynamic output droop resistance (ROD) based on * Output current step to no load with output voltage set at upper output dynamic voltage limit VONLD = VVID + VDERR - VRERR = 1.380 V * Output voltage prior to load change (at IOUT = IO) VOL = VONL - (IO x RO) = 1.292 V * ROD = (VONLD - VOL)/IO = (1.380 V - 1.292 V)/70 A = 1.25 m Number of phases (n) = 3 Switching frequency per phase (fSW) = 330 kHz
SOFT START DELAY TIME
The value of CSS sets the soft start time on initial power-up and, additionally, whenever the output voltage is modified by a change in the VID code. The ramp is generated with a 3.75 A internal current source during startup and by an 18.75 A internal current source during a VID code change. The value for CSS can be found using the following equations: During startup, CSS = 3.75 A x TD2 VVID (2)
where: TD2 is the desired soft start time. VVID is set by the VID inputs. The slew rate during a VID code change is five times faster than the startup slew rate (because the internal current source is five times larger).
*
CSS = 18.75 A x
TD VVID
The Advanced Micro Devices, AMD specification calls for a minimum slew rate of 2 mV/s for VID code changes. For example, if the VID code changes from 1.0 V to 1.2 V, then TD is 10 ms. This means CSS equals 9.375 nF. The closest standard capacitor value available is 10 nF.
* *
CURRENT-LIMIT LATCH-OFF DELAY TIMES
The start-up and current-limit delay times are determined by the capacitor connected to the DELAY pin. The first step is to set CDLY for the TD1 and TD3 delay times (see Figure 7). The DELAY ramp (IDELAY) is generated using a 15 A internal current source. The value for CDLY can be approximated using
C DLY = I DELAY x TD(x ) VDELAY (TH )
SETTING THE CLOCK FREQUENCY
The ADP3197 uses a fixed frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses as well as the sizes of the inductors, the input capacitors, and output capacitors. With n = 3 for three phases, a clock frequency of 1.32 MHz sets the switching frequency (fSW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 3 shows that to achieve a 1.32 MHz oscillator frequency, the correct value for RT is 130 k. Alternatively, the value for RT can be calculated using
(3)
where TD(x) is the desired delay time for TD1 and TD3. The DELAY threshold voltage (VDELAY(TH)) is given as 1.7 V. In this example, 2 ms is chosen for all delay times, which meets the AMD specifications (of not greater than 6 ms). Solving for CDLY gives a value of 17.6 nF. The closest standard value for CDLY is 18 nF. When the ADP3197 enters current limit, the internal current source changes from 15 A to 3.75 A. This makes the latch-off delay time four times longer than the start-up delay time. Longer latch-off delay times can be achieved by placing a resistor in parallel with CDLY.
RT =
1 n x f SW x 6 pF
(1)
where 6 pF is the internal IC component value. For good initial accuracy and frequency stability, a 1% resistor is recommended.
Rev. 0 | Page 17 of 32
ADP3197
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, using smaller inductors allows the converter to meet a specified peak-to-peak transient deviation with less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but more output capacitance is required to meet the same peak-topeak transient deviation. In any multiphase converter, a practical value for the peak-topeak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor.
The first decision in designing the inductor is choosing the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (from Micrometals, Inc., for example, or Kool Mu(R) from Magnetics) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type such as a potentiometer core (PQ, U, or E core) or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as * * Intusoft Magnetic Designer Software Designing Magnetic Components for High Frequency Dc-Dc Converters by William T. McLyman, Kg Magnetics, Inc., ISBN 1883107008
IR =
VVID x (1 - D ) f SW x L
(4)
Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage. L VVID x ROD x (1 - (n x D )) f SW x VRIPPLE
1.3 V x 1.25 m x (1 - 0.32 4 ) 330 kHz x 10 mV
Selecting a Standard Inductor
The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. * * * Coilcraft, Inc. Coiltronics/Div of Cooper Bussmann Sumida Corporation
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
L = 333 nH
If the resulting ripple voltage is less than what it is designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 400 nH inductor is a good starting point and gives a calculated ripple current of 8.78 A. The inductor should not saturate at the peak current of 41.06 A and should be able to handle the sum of the power dissipation caused by the average current of 36.7 A in the winding and core loss. Another important factor in the inductor design is the dc resistance (DCR), which is used for measuring the phase currents. A large DCR may cause excessive power losses, though too small a value may lead to increased measurement error. A good rule is to have the DCR (RL) be about 1 to 11/2 times the droop resistance (ROD). This example uses an inductor with a DCR of 1.875 m.
CURRENT SENSE AMPLIFIER
Most designs require the regulator output voltage, measured at the CPU pins, to droop when the output current increases. The specified voltage droop corresponds to a dc output resistance (RO), also referred to as a load line. The ADP3197 has the flexibility of adjusting RO independent of current-limit or compensation components, and it can also support CPUs that do not require a load line. For designs requiring a load line, the impedance gain of the CS amplifier (RCSA) must be greater than or equal to the load line. All designs, whether they have a load line or not, should keep RCSA 1 m. The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with Resistors RPH(x) (summers) and Resistor RCS and Capacitor CCS (filters). The impedance gain of the regulator is set by the following equations where RL is the DCR of the output inductors:
Designing an Inductor
Once the inductance and DCR are known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. Reasonable tolerances most manufacturers can meet are 15% inductance and 7% DCR at room temperature.
RCSA =
CCS =
RCS R PH ( x )
x RL
(6) (7)
L R L x RCS
The user has the flexibility to choose either RCS or RPH(x).
Rev. 0 | Page 18 of 32
ADP3197
However, it is best to select RCS equal to 100 k, and then solve for RPH(x) by rearranging Equation 6. Here, RCSA = 1 m because this is equal to the design load line.
2.
R PH ( x ) =
RL x RCS RCSA 1.875 m 1.0 m x 100 k = 187.5 k
3.
R PH ( x ) =
Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50C and 90C. These resistance values are called A (RTH(50C))/RTH(25C)) and B (RTH(90C))/RTH(25C)). The relative value of the NTC is always 1 at 25C. Find the relative value of RCS required for each of these temperatures. The relative value of RCS is based on the percentage change needed, which in this example is initially 0.39%/C. These temperatures are called r1. r1 = 1/(1 + TC x (T1 - 25C)) and r2 r2 = 1/(1 + TC x (T2 - 25C)) where: TC = 0.0039 for copper. T1 = 50C. T2 = 90C. From this, r1 = 0.9112 and r2 = 0.7978.
Next, use Equation 7 to solve for CCS.
C CS = 400 nH 1.875 m x 100 k = 2 nF
It is best to have a dual location for CCS in the layout so that standard values can be used in parallel to get as close as possible to the desired value. For best accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of two 1 nF capacitors in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 110 k and 140 k. The closest standard 1% value for RPH(X) is 187 k.
4.
Compute the relative values for RCS1, RCS2, and RTH using
INDUCTOR DCR TEMPERATURE CORRECTION
When the inductor DCR is used as the sense element and copper wire is used as the source of the DCR, the user needs to compensate for temperature changes of the inductor's winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of NTC thermistors, Resistor RCS1 and Resistor RCS2 are needed. See Figure 11 to linearize the NTC and produce the desired temperature tracking.
PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET RTH TO SWITCH NODES TO VOUT SENSE
RCS2 =
RCS1 =
( A - B ) x r1 x r2 - A x (1 - B ) x r2 + B x (1 - A) x r1 (8) A x (1 - B ) x r1 - B x (1 - A ) x r2 - ( A - B )
(1 - A ) 1 A - 1 - RCS2 r1 - RCS2
1 1 1 - 1 - RCS2 RCS1 (9)
RTH =
(10)
Calculate RTH = rTH x RCS, then select the closest value of thermistor available. Also, compute a scaling factor (K) based on the ratio of the actual thermistor value used relative to the computed one. K= 5. RTH ( ACTUAL ) RTH (CALCULATED ) (11)
ADP3197
CSCOMP
14
RPH1
RPH2
RPH3
Calculate values for RCS1 and RCS2 using Equation 12 and Equation 13. RCS1 = RCS x K x RCS1 (12) (13) RCS2 = RCS x ((1 - K) + (K x RCS2))
RCS1 CCS1 CCS2
RCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES
CSSUM
13
CSREF
06668-020
12
Figure 11. Temperature Compensation Circuit Values
In this example, RCS is calculated to be 114 k. Look for an available 100 k thermistor, 0603 size. One such thermistor is the Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these values, rCS1 = 0.3795, rCS2 = 0.7195, and rTH = 1.075. Solving for RTH yields 122.55 k, so 100 k is chosen, making K = 0.816. Next, find RCS1 and RCS2 to be 35.3 k and 87.9 k. Finally, choose the closest 1% resistor values, which yields a choice of 35.7 k and 88.7 k.
The following procedure and equations yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value: 1. Select an NTC based on type and value. Because the value is unknown, use a thermistor with a value close to RCS. The NTC should also have an initial tolerance of greater than 5%.
Rev. 0 | Page 19 of 32
ADP3197
Load Line Setting
For load line values greater than 1 m, RCSA can be set equal to RO, and the LLSET pin can be directly connected to the CSCOMP pin. When the load line value needs to be less than 1 m, two additional resistors are required. Figure 12 shows the placement of these resistors.
ADP3197
CSCOMP
By combining Equation 16 with Equation 14 and selecting minimum values for the resistors, the following equations result:
R LL2 =
I LIM x RO 50 A
(17)
R RLL1 = CSA - 1 x RLL 2 R O
(18)
Therefore, both RLL1 and RLL2 need to be in parallel and equal to less than 8.33 k.
14
CSSUM
13
CSREF
12
RLL1 LLSET
RLL2 OPTIONAL LOAD LINE SELECT SWITCH QLL
06668-021
Another useful feature for some VR applications is the ability to select different load lines. Figure 12 shows an optional MOSFET switch that allows this feature. Here, design for RCSA = RO(MAX) (selected with QLL on) and then use Equation 14 to set RO = RO(MIN) (selected with QLL off). For this design, RCSA = RO = 1 m. As a result, connect LLSET directly to CSCOMP; the RLL1 and RLL2 resistors are not needed.
11
OUTPUT OFFSET
The Advanced Micro Devices, AMD specification requires that at no load the nominal output voltage of the regulator be offset to a value higher than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing into the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 19.
RB = RB = VONL - VVID I FB 1.33 V - 1.3 V 15 A = 4.00 k
Figure 12. Load Line Setting Resistors
The two resistors, RLL1 and RLL2, set up a divider between the CSCOMP pin and CSREF pin. This resistor divider is input into the LLSET pin to set the load line slope RO of the VR according to the following equation: RO = RLL 2 x RCSA RLL1 + RLL 2 (14)
The resistor values for RLL1 and RLL2 are limited by two factors. * The minimum value is based on the loading of the CSCOMP pin. This pin's drive capability is 500 A, and the majority of this should be allocated to the CSA feedback. If the current through RLL1 and RLL2 is limited to 10% of this (50 A), the following limit can be placed for the minimum value for RLL1 and RLL2:
(19)
The closest standard 1% resistor value is 4.00 k.
COUT SELECTION
The required output decoupling for the regulator is typically recommended by AMD for various processors and platforms. Use simple design guidelines to determine the requirements. These guidelines are based on having both bulk capacitors and ceramic capacitors in the system. First, select the total amount of ceramic capacitance. This is based on the number and type of capacitor used. The best location for ceramic capacitors is inside the socket. Other capacitors can be placed along the outer edge of the socket. Combined ceramic values of 30 F to 100 F are recommended, usually made up of multiple 10 F or 22 F capacitors. Select the number of ceramics and find the total ceramic capacitance (Cz). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when the user considers the VID on-thefly voltage stepping of the output (voltage step VV in time tV with an error of VERR).
RLL1 + RLL2
I LIM x RCSA 50 x 10 -6
(15)
Here, ILIM is the current-limit current, which is the maximum signal level that the CSA responds to. * The maximum value is based on minimizing induced dc offset errors based on the bias current of the LLSET pin. To keep the induced dc error less than 1 mV, which makes this error statistically negligible, place the following limit to the parallel combination of RLL1 and RLL2:
RLL1 x RLL2 1 x 10 -3 = 8.33 k RLL1 + RLL2 120 x 10 -9
(16)
When selecting the resistors, it is best to minimize their values to reduce the noise and parasitic susceptibility of the feedback path.
Rev. 0 | Page 20 of 32
ADP3197
A lower limit is based on meeting the capacitance for load release for a given maximum load step (IO) and a maximum allowable overshoot. The total amount of load release voltage is given as VO = IO x ROD. L x IO C X ( MIN ) - CZ nx R xV VID OD
C X ( MAX )

2 - 1 - C Z
In this example, LX is approximately 240 pH for the 10 Al-Poly capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors needs to be increased, or lower ESL bulks must be used if there is excessive undershoot during a load transient. For this multimode control technique, all ceramic designs can be used providing the conditions of Equation 20 through Equation 23 are satisfied.
(20) (21)
V nKRO V L x V x 1 + tV VID x 22 V nK RO VVID L V
POWER MOSFETS
For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3120A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE equal to approximately 10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3197, currents are balanced between phases; thus, the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, Equation 24 shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO).
I PSF = (1 - D ) x O n SF 1 n IR + x 12 n SF
2
V where K = -1n ERR V V

To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the dynamic input droop resistance (ROD). If CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). This example uses 18, 10 F 1206 MLC capacitors (CZ = 180 F). The VID on-the-fly step change is 1.3 V to 0.6 V (making VV = 0.7 V) in 100 s with a settling error of 2.5 mV. The maximum allowable load release overshoot for this example is 3%. Therefore, solving for the bulk capacitance yields C X ( MIN ) 400 nH x 70 A - 180 F = 5.564 mF (22) 3 x 1.25 m x 1.3 V

2
x R DS ( SF )
(24)
C X ( MAX )
3 x 3.5 x (1.25 m ) x 1.3 V
2 2
400 nH x 700 mV
x
2 100 s x 1.3 V x 3 x 3.5 x 1.25 m - 1 - 1+ 700 mV x 400 nH 180 F = 19.23 mF
Knowing the maximum output current being designed for and the maximum allowed power dissipation, the user can find the required RDS(ON) for the MOSFET. For D-Pak MOSFETs up to an ambient temperature of 50C, a safe limit for PSF is 1 W to 1.5 W at 120C junction temperature. Thus, for this example (100 A maximum), RDS(SF) (per MOSFET) is less than 7.5 m. This RDS(SF) is also at a junction temperature of about 120C. As a result, users need to account for these conditions when selecting a low-side MOSFET. This example uses two lower-side MOSFETs at 4.8 m, each at 120C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3110A). The output impedance of the driver is approximately 2 and the typical MOSFET input gate resistances are about 1 to 2 . Therefore, a total gate capacitance of less than 6000 pF should be adhered to.
where K = 3.5. Using 10, 560 F Al-Poly capacitors with a typical ESR of 6 m each yields CX = 5.6 mF with an RX = 0.6 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit high frequency ringing during a load change. This is tested using L X CZ x RO 2 x Q 2 L X 180 F x (1.25 m )2 x 2 = 562 pH (23)
where Q2 is limited to 2 to ensure a critically damped system.
Rev. 0 | Page 21 of 32
ADP3197
Because two MOSFETs are in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off and to the current and voltage being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, Equation 25 provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs.
PS ( MF ) = 2 x f SW x VCC x I O n MF
Finally, consider the power dissipation in the driver for each phase. This is best expressed as QG for the MOSFETs and is given by Equation 27, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. f PDRV = SW x (n MF x Q GMF + nSF x QGSF ) + I CC x VCC (27) 2 x n Also shown is the standby dissipation factor (ICC x VCC) of the driver. For the ADP3110A, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, there is 297 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3110A data sheet for more details.
x RG x
n MF x C ISS n
(25)
where: RG is the total gate resistance (2 for the ADP3110A and about 1 for typical high speed switching MOSFETs, making RG = 3 ). CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not help the switching loss per MOSFET because the additional gate capacitance slows switching. Use lower gate capacitance devices to reduce switching loss. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET:
I O PC ( MF ) = D x nMF n x IR + 1 x 12 nMF
2
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Equation 28 is used for determining the optimum value.
RR =
AR x L 3 x AD x RDS x C R 0.2 x 400 nH = 444 k 3 x 5 x 2.4 m x 5 pF
(28)

2
x RDS ( MF )
RR =
(26)
Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-Pak) when combining the switching and conduction losses. For this example, an NTD40N03L is selected as the main MOSFET (six total; nMF = 6), with CISS = 584 pF (maximum) and RDS(MF) = 19 m (maximum at TJ = 120C). An NTD110N02L is selected as the synchronous MOSFET (six total; nSF = 6), with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 m (maximum at TJ = 120C). The synchronous MOSFET CISS is less than 3000 pF, satisfying this requirement. Solving for the power dissipation per MOSFET at IO = 100 A and IR = 12.55 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. A guideline to follow is to limit the MOSFET power dissipation to 1 W. The values calculated in Equation 25 and Equation 26 comply with this guideline.
where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. The internal ramp voltage magnitude can be calculated by using
VR = AR x (1 - D ) x VVID R R x C R x f SW 0.2 x (1 - 0.108 ) x 1.3 V = 317 mV 444 k x 5 pF x 330 kHz
(29)
VR =
The size of the internal ramp can be made larger or smaller. If it is made larger, stability and noise rejection improve, but transient degrades. Likewise, if the ramp is made smaller, transient response improves at the sacrifice of noise rejection and stability. The factor of 3 in the denominator of Equation 28 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
Rev. 0 | Page 22 of 32
ADP3197
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input:
VRT = 2 x (1 - n x D ) 1 - nx f xC x R X SW O VR
For the ADP3197, the maximum COMP voltage (VCOMP(MAX)) is 4.0 V, and the COMP pin bias voltage (VBIAS) is 1.1 V. In this example, the maximum duty cycle is 0.61 and the peak current is 62 A. The limit of the peak per-phase current described previously during the secondary current limit is determined by VCOMP (CLAMPED ) - V BIAS (34) I PHLIM A D x R DS ( MAX ) For the ADP3197, the current balancing amplifier gain (AD) is 5 and the clamped COMP pin voltage is 2 V. Using an RDS(MAX) of 2.8 m (low-side on resistance at 150C) results in a per-phase peak current limit of 64 A. This current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur.
(30)
In this example, the overall ramp signal is 0.46 V. However, if the ramp size is smaller than 0.5 V, increase the ramp size to at least 0.5 V by decreasing the ramp resistor for noise immunity. Because there is only 0.46 V initially, a ramp resistor value of 444 k is chosen for this example, yielding an overall ramp of 0.51 V.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3197 is set with a constant current source flowing out of the ILIMIT pin, which sets up a voltage (VLIM) across RLIM with a gain of 82.6 mV/V (ALIM). Thus, increasing RLIM now increases the current limit. RLIM can be found using
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3197 allows the best possible response of the regulator output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the static output droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and minimizes the output decoupling. Because of the multimode feedback structure of the ADP3197, the feedback compensation must be set to make the converter output impedance work in parallel with the output decoupling to make the load look entirely resistive. Compensation is needed for several poles and zeros created by the output inductor and the decoupling capacitors (output filter). A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 35 to Equation 39 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning the ADP3197 section).
R LIM =
VCL ALIM x I ILIMIT
=
I LIM x RCSA x R REF 82.6 mV
(31)
Here, ILIM is the peak average current limit for the supply output. The peak average current is the dc current limit plus the output ripple current. In this example, choosing a dc current limit of 159 A and having a ripple current of 12.55 A gives an ILIM of 171.55 A. This results in an RLIM = 207.6 k, for which 205 k is chosen as the nearest 1% value. The per-phase initial duty cycle limit and peak current during a load step are determined by D MAX = D x
I PHMAX
VCOMP ( MAX ) - V BIAS V RT
(32) (33)
D MAX (VIN - VVID ) x f SW L
Rev. 0 | Page 23 of 32
ADP3197
Computing the Time Constants
First, compute the time constants for all the poles and zeros in the system using Equation 35 to Equation 39. R E = n x RO + A D x R DS + R L x VRT VVID + 2 x L x (1 - n x D ) x VRT n x C X x RO x VVID 2 x 320 nH x (1 - 0.432 ) x 0.51 V 4 x 5.6 mF x 1 m x 1.3 V
R E = 4 x 1 m + 5 x 2.4 m +
1.4 m x 0.51 V 1.3 V
+
= 22.9 m
(35)
TA = C X x (RO - R' ) +
240 pH 1 m - 0.5 m L X RO - R' x = 5.6 mF x (1 m - 0.5 m ) + x = 3.00 s RO RX 1 m 0.6 m
(36)
TB = (R X + R' - RO ) x C X = (0.6 m + 0.5 m - 1 m ) x 5.6 mF = 560 ns A x RDS 5 x 2.4 m 0.51 V x 320 nH - VRT x L - D 2 x f SW 2 x 330 kHz = 5.17 s TC = = VVID x RE 1.3 V x 22.9 m
2 C X x C Z x RO
(37)
(38)
TD =
C X x (RO - R' ) + C Z x RO
=
5.6 mF x (1 m - 0.5 m ) + 180 F x 1 m
5.6 mF x 180 F x (1 m )2
= 338 ns
(39)
where: R' is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total low-side MOSFET on resistance per phase. AD = 5. VRT = 0.51 V. R' 0.5 m (assuming a 4-layer, 1 oz motherboard). LX = 240 pH for the 10 Al-Poly capacitors. The compensation values can then be solved using
CA =
RA =
n x RO x TA RE x RB
=
4 x 1 m x 3.00 s 22.9 m x 1.00 k
= 524 pF
(40) (41)
5.17 s TC = = 9.87 k C A 524 pF
CB = C FB =
TB 560 ns = = 560 pF R B 1.00 k TD 338 ns = = 34.2 pF R A 9.87 k
(42)
(43)
These are the starting values prior to tuning the design that account for layout and other parasitic effects (see the Tuning the ADP3197 section). The final values selected after tuning are CA = 560 pF RA = 10.0 k CB = 560 pF CFB = 27 pF
Rev. 0 | Page 24 of 32
ADP3197
CIN SELECTION AND INPUT CURRENT di/dt REDUCTION
In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by
I CRMS = D x I O x 1 -1 N xD (44) I CRMS = 0.108 x 110 A x 1 - 1 = 17.2 A 3 x 0.108 An additional fixed resistor in parallel with the thermistor allows tuning of the trip point temperatures to match the hottest temperature in the VR, when the thermistor itself is directly sensing a proportionately lower temperature. Setting this resistor value is best accomplished with a variable resistor during thermal validation and then fixing this value for the final design. Additionally, a 0.1 F capacitor should be used for filtering noise.
SHUNT RESISTOR DESIGN
The ADP3197 uses a shunt to generate 5 V from the 12 V supply range. A trade-off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 14 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages.
550 500 450 PSHUNT RSHUNT () 400 350 300 250 200 150 7.0 RSHUNT PSHUNT (W) 0.35 0.30 0.25 0.20 0.15 0.10 11.0 0.50 0.45 0.40
The capacitor manufacturer's ripple-current ratings are often based on only 2000 hours of life. As a result, it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors can be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by three 2700 F, 16 V aluminum electrolytic capacitors and eight 4.7 F ceramic capacitors. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/s, an additional small inductor (L > 370 nH at 18 A) should be inserted between the converter and the supply bus. This inductor also acts as a filter between the converter and the primary power source.
THERMAL MONITOR DESIGN
A thermistor is used on the TTSENSE input of the ADP3197 for monitoring the temperature of the VR. A constant current of 123 A is sourced out of this pin and runs through a thermistor network such as the one shown in Figure 13.
ADP3197
OPTIONAL TEMPERATURE ADJUST RESISTOR
32
7.5
8.0
8.5
9.0 VIN (UVLO)
9.5
10.0
10.5
Figure 14. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage
The maximum power dissipated is calculated using Equation 45.
PMAX =
(V
IN ( MAX )
- VCC ( MIN )
)
2
VRHOT
R SHUNT
(45)
31
TTSENSE
RTTSENSE
Figure 13. VR Thermal Monitor Circuit
A voltage is generated from this current through the thermistor and sensed inside the IC. When the voltage reaches 0.71 V, the VRHOT is set. This corresponds to RTTSENSE value of 6.58 k. These values correspond to a thermistor temperature of ~100C and ~110C when using the same type of 100 k NTC thermistor used in the current sense amplifier.
06668-022
PLACE THERMISTOR NEAR CLOSEST PHASE
0.1F
where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP3197. This is specified as 4.75 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W.
Rev. 0 | Page 25 of 32
06668-019
ADP3197
TUNING THE ADP3197
1. 2. Build a circuit based on the compensation values computed from the design spreadsheet. Hook up the dc load to the circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 14. Measure the output waveform (use dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 15.
DC Load Line Setting
Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2 using Equation 46 and Equation 49. V - V FLCOLD (46) R CS2 ( NEW ) = R CS2 (OLD ) x NL V NL - V FLHOT 5. Repeat Step 4 until the cold and hot voltage measurements remain the same. 6. Measure the output voltage from no load to full load using 5 A steps. Compute the load line slope for each change, and then average to find the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 m, use Equation 47 to adjust the RPH values. R (47) R PH ( NEW ) = R PH (OLD ) x OMEAS RO 8. Repeat Step 6 and Step 7 to check the load line. Repeat adjustments if necessary. 9. When the dc load line adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. 3.
VACDRP VDCDRP
Figure 15. AC Load Line Waveform
15. Use the horizontal cursors to measure VACDRP and VDCDRP, as shown in Figure 15. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 49 to adjust CCS. Users may need to parallel different values to get the right one because limited standard capacitor values are available. It is a good idea to have locations for two capacitors in the layout for this. V (48) C CS ( NEW ) = C CS (OLD ) x ACDRP V DCDRP 17. Repeat Step 11 to Step 13 and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. Set the dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means that VACDRP and VDCDRP are equal.
AC Load Line Setting
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div.
RCS1( NEW ) =
RCS1(OLD ) x RTH (25 C ) + RCS1(OLD ) - RCS2( NEW ) x RCS1(OLD ) - RTH (25 C )
(
1 RCS1(OLD ) + RTH (25 C )
06668-016
)(
)
-
1 RTH (25 C )
(49)
Rev. 0 | Page 26 of 32
ADP3197
Initial Transient Setting
18. With the dynamic load still set at the maximum step size, expand the scope time scale to either 2 s/div or 5 s/div. The waveform can have two overshoots and one minor undershoot (see Figure 16). Here, VDROOP is the final desired value. Because the ADP3197 turns off all of the phases (switches inductors to ground), no ripple voltage is present during load release. Therefore, the user does not have to add headroom for ripple. This allows load release VTRANREL to be larger than VTRAN1 by the amount of ripple and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications.
VDROOP
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
VTRAN1 VTRAN2
06668-017
Figure 16. Transient Setting Waveform
19. If both overshoots are larger than desired, try making the adjustments using the following suggestions: * * * Make the ramp resistor larger by 25% (RRAMP). For VTRAN1, increase CB or increase the switching frequency. For VTRAN2, increase RA and decrease CA by 25%.
For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3197) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3197 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3197 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and the CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (as described in the Power Circuitry Recommendations section).
If these adjustments do not change the response, the design is limited by the output decoupling. Check the output response every time a change is made, and check the switching nodes to ensure that the response is still stable. 20. For load release (see Figure 17), if VTRANREL is larger than the allowed overshoot, there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be made smaller. When changing inductors, start the design again using a spreadsheet and this tuning procedure.
VTRANREL
VDROOP
Figure 17. Transient Setting Waveform
06668-018
Rev. 0 | Page 27 of 32
ADP3197
Power Circuitry Recommendations
The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended that vias be used liberally, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat-sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.
Rev. 0 | Page 28 of 32
ADP3197 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
9
0.25 MIN 3.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3197JCPZ-RL1
1
Temperature Range 0C to 85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option CP-32-2
Ordering Quantity 2,500
Z = RoHS Compliant Part.
Rev. 0 | Page 29 of 32
ADP3197 NOTES
Rev. 0 | Page 30 of 32
ADP3197 NOTES
Rev. 0 | Page 31 of 32
ADP3197 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06668-0-5/07(0)
Rev. 0 | Page 32 of 32

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